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Daily Archives: Friday, October 15, 2010
>Data IC CMOS
>
>Data IC TTL
>Dalam “buku Data IC TTL” sinopsis apa artinya dalam katalog Prancis, akan di lampikan jenis jenis IC serta Layout IC TTL ( Transistor Transistor Logic )
Rangkaian yang ditemui di Industri :
Teknologi bipolar dan MOS sampai sekarang digunakan dalam sirkuit industri.Bahwa untuk pemeliharaan atau realisasi, adalah penting untuk mengetahui bukan teknologi saja, tetapi juga persediaan dari sirkuit dengan fungsi mereka.Setiap produsen menggunakan kode yang mencetak pada kasus-kasus untuk dapat mengidentifikasi mereka. Masih kode ini harus diketahui.Ini adalah peran tokoh 1 dan 2 yang memberikan arti dari kode nama dari TTL sirkuit logis dan C-MOS.
Dua paragraf yang mengikuti masing-masing memberikan fungsi dan jahitan sirkuit logis TTL (bipolar), sedangkan dua terakhir mengejar tujuan yang sama tetapi dalam teknologi C. MOS.
To know certain stitchings ortheir connections of the integrated circuits, it is enough to pass your pointeron the bonds hereafter:
| 7400 N | Quadruple door NOT – AND at 2 entries |
| 7401 N | Quadruple door NOT – AND at 2 entries with open collector |
| 7402 N | Quadruple door NOT – OR at 2 entries |
| 7403 N | Quadruple door NOT – AND at 2 entries with open collector |
| 7404 N | 6 reversers |
| 7405 N | 6 reversers with open collector |
| 7406 N | 6 stages of attack reverser to open collector for 40 my |
| 7407 N | 6 stages of attack to open collector for 40 my |
| 7408 N | Quadruple door AND at 2 entries |
| 7409 N | Quadruple door AND at 2 entries with open collector |
| 7410 N | Triple carries NOT – AND at 3 entries |
| 7411 N | Triple carries AND to 3 entry |
| 7412 N | Triple carries NOT – AND at 3 entries with open collector |
| 7413 N | Double door NOT – AND at 4 entries |
| 7414 N | 6 reversers trigger |
| 7416 N | 6 reversers of powers to open collector |
| 7417 N | 6 stages of attack to open collector for 40 my |
| 7420 N | Double door NOT – AND at 4 entries |
| 7422 N | Double door NOT – AND at 4 entries with open collector |
| 7423 N | Double door NOT – OR at 4 entries expansible and strobe |
| 7425 N | Double door NOT – OR at 4 entries and strobe |
| 7426 N | Quadruple door NOT – AND with 2 entries – High voltage |
| 7427 N | Triple carries NOT – OR at 3 entries |
| 7428 N | Quadruple NOR door at 2 entries |
| 7430 N | Carry NOT – AND at 8 entries |
| 7432 N | Quadruple door OR at 2 entries |
| 7437 N | Quadruple door NOT – AND of power at 2 entries |
| 7438 N | Quadruple door NOT – AND of power at 2 entries and open collector |
| 7440 N | Double door NOT – AND of power at 4 entries |
| 7442 N | Decimal decoder BCD |
| 7443 N | Decoder excesses of 3 – decimal |
| 7444 N | Decoder excesses of 3 Gray – decimal |
| 7445 N | Decimal decoder BCD with open collector for 80 my and 30 V or 15 V |
| 7446 AN | Decoder BCD 7 segments with open collector with 30 V/20 my |
| 7447 AN | Decoder BCD 7 segments with open collector with 30 V/20 my |
| 7448 N | Decoder BCD 7 segments |
| 7450 N | Double door AND/OR – NOT to 2 X 2 entries |
| 7451 N | Double door reverser AND/OR – NOT to 2 X 2 entries |
| 7453 N | Carry reverser AND/OR – NOT to 4 X 2 entries expansible |
| 7454 N | Carry reverser AND/OR – NOT to 4 X 2 entries |
| 7460 N | Double door of multiplication at 4 entries |
| 7470 N | Flip-flop JK to 2 X 3 entries |
| 7472 N | Main flip-flop slave with 2 X 3 entries |
| 7473 N | Main flip-flop slave with entry reset |
| 7474 N | Double Flip-flop D synchronous |
| 7475 N | Quadruple Flip-flop D asynchronous |
| 7476 N | Double main Flip-flop JK slave with entries set and reset |
| 7480 N | Full adder with 1 bit |
| 7481 N | Memory with 16 bits writing/reading |
| 7482 N | Full adder with 2 bits |
| 7483 AN | Full adder with 4 bits |
| 7484 AN | Memory with 16 bits writing/reading at 2 entries of writing and reading |
| 7485 N | Binary comparator with 4 bits |
| 7486 N | Quadruple door OR Exclusive |
| 7489 N | Memory with 64 bits writing/reading with open collector |
| 7490 AN | Decimal scaler |
| 7491 AN | Register with shift with 8 bits series |
| 7492 N | Divider by 12 |
| 7493 N | Binary counter |
| 7494 N | Register with shift 4 bits at parallel entry |
| 7495 AN | Register with shift 4 bits entered and 4 parallel ports |
| 7496 N | Register with parallel shift 5 bits |
| 7497 N | Divider of synchronous binary frequency programmable 6 bits |
| 74100 N | Octo-Flip-failure D |
| 74107 N | Double main Flip-flop JK slave with entry reset |
| 74110 N | Main flip-flop JK slave with blocking of entry |
| 74111 N | Double main Flip-flop JK slave with blocking of entry |
| 74118 N | Sixfold Flip-flop RS at common entry of reset |
| 74120 N | Double synchronization of impulses |
| 74121 N | Monostable |
| 74122 N | Monostable redéclenchable at entry reset |
| 74123 N | Double monostable redéclenchable at entry reset |
| 74125 N | 4 doors YES at exits 3 states |
| 74132 N | Quadruple Trigger de Schmitt NOT – AND at 2 entries |
| 74141 AN | Decimal decoder BCD for tubes of posting |
| 74142 N | Decimal scaler and ordering of NIXIE |
| 74145 N | Decimal decoder BCD with open collector for 80 my and 30 V or 15 V |
| 74148 N | 8 To 3 Line Priority Encoder |
| 74150 N | Selector of data 16 bits/multiplexer |
| 74151 N | Selector of data 8 bits/multiplexer |
| 74153 N | Double selector of data 4 bits/multiplexer |
| 74154 N | Binary decoder 4 bits/demultiplexer |
| 74155 N | Double binary decoder 2 bits/demultiplexer |
| 74156 N | Double binary decoder 2 bits/demultiplexer |
| 74157 N | Quadruple selector of information 2 bits/multiplexer |
| 74160 N | Synchronous decimal scaler at entry of set and reset |
| 74161 N | Synchronous decimal scaler at entry of set and reset |
| 74162 N | Synchronous binary counter 4 bits at entry of set and reset |
| 74163 N | Synchronous binary counter 4 bits at entry of set and reset |
| 74164 N | Register with shift 8 bits at parallel port |
| 74165 N | Register shift 8 bits at parallel entry |
| 74166 N | Register with synchronous shift 8 bits at parallel entry |
| 74167 N | Divider of frequencies, decimal |
| 74170 N | Memory with 16 bits writing/reading with words to 4 bits |
| 74174 N | Sixfold Flip-flop D at entry of reset |
| 74175 N | Quadruple Flip-flop D synchronous |
| 74180 N | Parity check 8 bits |
| 74181 N | Arithmetic logical unit 4 bits |
| 74184 N | Binary converter BCD 6 bits |
| 74185 AN | Binary converter BCD 6 bits |
| 74190 N | Reversible decimal scaler for synchronous counting chain |
| 74191 N | Reversible binary counter for synchronous counting chain |
| 74192 N | Meter decimal discounting machine with set and reset |
| 74193 N | Binary meter discounting machine with set and reset |
| 74194 N | Register with synchronous 4 bits right-hand side/left parallel shift |
| 74195 N | Register with synchronous shift parallel 4 bits with entry JK |
| 74196 N | Decimal scaler 50 MHz with entry of set and reset |
| 74197 N | Binary counter 50 MHz with entry of set and reset |
| 74198 N | Register with synchronous shift 8 bits at entry and port parallel |
| 74199 N | Register with synchronous shift 8 bits parallel at entry JK |
| 74LS241 | Driver of bus not reverser |
| 74LS242 | Quad drunk transceiver inverting |
| 74LS243 | 4 transcoders not reverser 3 states |
| 81LS95 | 74795 : Octal Buffer with Three-State Outputs (74LS795 is equivalent to 81LS95) |
| 81LS97 | 74797 : Octal Buffer with Three-State Outputs (74LS797 is equivalent to 81LS97) |
>Flip-flop D
>
Nama flip-flop ini berasal dari Delay. Flip-flop ini mempunyai hanya satu masukan, yaitu D. Jenis flip-flop ini sangat banyak dipakai sebagai sel memori dalam komputer. Pada umumnya flip-flop ini dilengkapi masukan penabuh se-perti ditunjukkan pada Gambar 6.10. Keluaran flip-flop D akan mengikuti apapun keadaan D pada saat penabuh aktif, yaitu: Q+ = D. Perubahan itu terjadi hanya apabila sinyal penabuh dibuat berlogika 1 (CP=1) dan tentunya akan terjadi sesudah selang waktu tertentu, yaitu selama tundaan waktu pada flip-flop itu. Bila masukan D berubah selagi CP = 0, maka Q tidak akan terpengaruh. Keadaan Q selama CP= 0 adalah keadaan masukan D tepat sebelum CP berubah menjadi 0. Dikatakan keadaan keluaran Q dipalang (latched) pada keadaan D saat perubahan CP dari aktif ke tak-aktif.
Dapat dilihat bahwa sebenarnya flip-flop D berfungsi seperti apa yang dilakukan oleh flip-flop JK bila masukan masukan K dihubungkan dengan komplemen masukan J.
